Omnidirectional WPT and data communication for electric air vehicles: feasibility study

This paper investigates the feasibility of using the three dimensional omnidirectional inductive channel for power transfer and as a power line communication PLC for ground-based vehicle, electric air vehicle or space applications, the simulation results is performed by the advanced design system software using lumped equivalent circuit model. The power transfer efficiency determined based on multiport scattering (S)-parameters numerical simulation results while the theoretical channel capacity is calculated based on Matlab software as a function of the coupling coefficient considering an additive white Gaussian noise . Furthermore, the magnetic field distribution is evaluated as function of the misalignment angle θ between the receiver and the three orthogonal transmitters coils

Characterization of a Two-Coil Channel Considering Misalignment Scenarios

Publisher Copyright: © 2022 by the authors. Licensee MDPI, Basel, Switzerland.WPT system performances highly depend on the misalignment scenarios of the transmitter or the receiver coil. In this contribution, the authors analyze the effect of the misalignment influencing factors of the integrated WPT-PLC system receiving coil on the system performances. The simulations and experimental analysis are based on power efficiency and channel capacity metrics. The simulations are performed using finite element calculations in COMSOL Multiphysics and Advanced Design System (ADS) from Keysight technology. By analyzing the results, maximum transferred power is reached under resonance conditions. For instance, the calculated efficiencies versus the misalignment cases of the WPT-PLC system varies (η = 86% to 60%) when d = [3 cm to 7 cm], s = [3 cm to 9 cm], and for a tilt angle θ ≤ 20 deg, while the optimal data rate C(bps) is achieved while appealing different data access points and under reasonable SNR value.publishersversionpublishe

A concurrent error detection based fault-tolerant 32 nm XOR-XNOR circuit implementation

As modern processors and semiconductor circuits move into 32 nm technologies and below, designers face the major problem of process variations. This problem makes designing VLSI circuits harder and harder, affects the circuit performance and introduces faults that can cause critical failures. Therefore, fault-tolerant design is required to obtain the necessary level of reliability and availability especially for safety-critical systems. Since XOR-XNOR circuits are basic building blocks in various digital and mixed systems, especially in arithmetic circuits, these gates should be designed such that they indicate any malfunction during normal operation. In fact, this property of verifying the results delivered by a circuit during its normal operation is called Concurrent Error Detection (CED). In this paper, we propose a CED based fault- tolerant XOR-XNOR circuit implementation. The proposed design is performed using the 32 nm process technology.published_or_final_versio

Performance Enhancement of Large Crossbar Resistive Memories With Complementary and 1D1R-1R1D RRAM Structures

The paper proposes novel solutions to improve the signal and thermal integrity of crossbar arrays of Resistive Random-Access Memories, that are among the most promising technologies for the 3D monolithic integration. These structures suffer from electrothermal issues, due to the heat generated by the power dissipation during the write process. This paper explores novel solutions based on new architectures and materials, for managing the issues related to the voltage drop along the interconnects and to thermal crosstalk between memory cells. The analyzed memristor is the 1 Diode - 1 Resistor memory. The two architectural solutions are given by a reverse architecture and a complementary resistive switching one. Compared to conventional architectures, both of them are also reducing the number of layers where the bias is applied. The electrothermal performance of these new structures is compared to that of the reference one, for a case-study given by a 4 × 4 × 4 array. To this end, a full-3D numerical Multiphysics model is implemented and successfully compared against other models in literature. The possibility of changing the interconnect materials is also analyzed. The results of this performance analysis clearly show the benefits of moving to these novel architectures, together with the choice of new materials

The DFA/DFT‐based hacking techniques and countermeasures: Case study of the 32‐bit AES encryption crypto‐core

Abstract Integrated circuits (ICs) design plays a significant role in the embedded‐system performance, reliability and security. Thus, the constant advances in very large‐scale integration technology have led to design and manufacture of very complex ICs based on the System on a Chip (SoC) approach design. Therefore, the embedded system testing is considered earlier during the design process and testability is used as one of the objectives for evaluating safety‐critical embedded system designs. On the other hand, embedded systems used in critical applications execute security‐critical commands and collect sensitive data protected by cryptographic keys and authentication codes. The data and the unauthorised access of these embedded devices is an obvious target for attackers in order to obtain control or extract internal data. In this paper we consider that by using Design for Testability (DFT) approaches an attacker can control and affect a security‐critical embedded system. Thus, the authors focus on the DFT approach, as a means of violation of the security and confidentiality of embedded systems with security‐critical goals. In addition, with or without insertion of DFT circuitry, the crypto‐core is always exposed to the powerful differential fault analysis (DFA) attack. Here, a 32‐bit AES crypto‐core is used as a case study in order to analyse the DFA‐ and the DFT‐based Hacking techniques. A countermeasure was performed in order to avoid any scan or even DFA attack attempt

Adoption of a Secure ECC-based RFID Authentication Protocol

International audienc

Analysis of Pre-Driver and Last-Stage Power—Ground-Induced Jitter at Different PVT Corners

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct P/G DC supply voltages at the pre-driver (i.e., VDD/VSS) and last stage (i.e., VDDQ/VSSQ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions

Enhanced I/O Buffer Predriver Modeling under Power/Ground Supply Voltage Variation

This paper presents I/O buffer nonlinear behavioral modelling that accounts for timing distortion introduced by nonlinear switching behavior of the predriver electrical circuit under power and ground supply voltage (PGSV) variation. Model structure and I/O device characterization along with extraction procedure are described. I/O buffer’s last stage is modelled as nonlinear current-voltage (I-V) and capacitance voltage (C-V) functions capturing the nonlinear dynamic impedances of the pull-up and pull-down transistors. The predriver’s mathematical model structure is derived from the analysis of the large signal electrical circuit switching behavior. Accordingly, a generic and surrogate multilayer neural network (NN) structure is considered in this work. Timing series data, which reflects the observed the nonlinear switching behavior of the multistage predriver’s circuit PGSV variations, is used to train the NN model. The proposed model is implemented in time domain solver and validated against reference transistor level (TL) model and the state of the art input-output buffer information specification (IBIS) behavioral model under different scenarios. The jitter analysis is performed using the eye diagram tool through analyzing its different metrics values